16-week Board-to-Bitstream Bundle

What you get

  • A review of the FPGA side of your schematic in the first week.

  • A functional block diagram and architecture to be agreed upon before any RTL is written.

  • Fully implemented and simulated VHDL, with constraints and a timing-closed bitstream.

  • Tested on your hardware against acceptance tests you set.

  • Full documentation and a handover session for your team.

  • NDA signed before we start; you own all project IP.

  • Your code stays on your systems, or in an encrypted private repository you control/have access to.

How it works

  • Week 1 - Review FPGA portion of the client’s schematic

    • Pinout

    • I/O banks

    • Clocking

    • Configuration

  • Weeks 2-3 - Functional block diagram and architecture

    • Produce and agree the block diagram and architecture before any code is written

  • Weeks 4-11 - VHDL implementation and simulation

    • Implement every module in VHDL

    • Perform functional and stress simulations

  • Weeks 12-14 - Bitstream generation and hardware testing

    • Achieve timing closure

    • Generate final bitstreams

    • Test on the hardware agreed upon (custom or development kit)

  • Weeks 15-16 - Documentation, deliverables and handover

    • Complete architecture documentation

    • Deliver source code

    • Conduct a handover session

Guarantee

If design does not pass tests after 16 weeks then work continues free of charge until it does.

Pricing

ZAR 400 000

This covers the full 16-week project: schematic review, block diagram, implemented and simulated VHDL, testing on your board and complete documentation.

Add-ons

  • High-speed interfaces (Ethernet, PCIe, DDR): +ZAR 50 000

  • DSP or RF work: +ZAR 50 000

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